Physical Design Engineer
Texas Instruments
Change the world. Love your job.
We enable next generation of Audio-Video in cars whether it is to enable self-driving in an ADAS system or rear-seat entertainment in an IVI system. You will be part of the team enabling high end experience in the future generation of cars.
In this position, you will be working on the physical design of high-speed mixed-signal SerDes circuits using state-of-the art process technology. You will be working on multi-million gate design with complex clock-trees and high-speed interfaces to Analog.
Your responsibilities will include synthesis, various steps of physical design such as floorplan, placement, clock-tree synthesis and debug, routing, timing closure, power analysis, IR-drop, EM-checks, physical verification such as DRC, LVS, Antenna etc.
As a physical design engineer, you will be responsible for tapeout in Digital-on-top flows or delivery of timing clean sub-chip for top-level integration in Analog-on-Top flows. You will be responsible to ensure the device meets the spec. requirement with regards to Power, Performance, and Area. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.
This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.
- Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.
- We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI
- Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us.
TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.
Minimum requirements:
- 12 years of relevant experience
- Expertise with Cadence toolset for PnR, Timing Analysis and Synthesis
- Familiarity with multi-clock domain Clock-Tree Synthesis (CTS) and debugging
- Strong ability to understand physical realizations of logic structures and clocking
- Experience through all aspects of digital sub-chip delivery including power, IR, EM, DRC, LVS etc
- Skilled in writing TCL scripts for editing the netlist for cloning, load balancing and ECOs
- Ability to work with multi-million gate designs
- Ability to solve problems using a systematic approach
Preferred qualifications:
- Demonstrated strong analytical and problem-solving skills
- Strong verbal and written communication skills
- Ability to work in teams and collaborate effectively with people in different functions
- Strong time management skills that enable on-time project delivery
- Demonstrated ability to build strong, influential relationships
- Ability to work effectively in a fast-paced and rapidly changing environment
- Ability to take the initiative and drive for results
Minimum requirements:
- 8 years of relevant experience
- Expertise with Cadence toolset for PnR, Timing Analysis and Synthesis
- Familiarity with multi-clock domain Clock-Tree Synthesis (CTS) and debugging
- Strong ability to understand physical realizations of logic structures and clocking
- Experience through all aspects of digital sub-chip delivery including power, IR, EM, DRC, LVS etc
- Skilled in writing TCL scripts for editing the netlist for cloning, load balancing and ECOs
- Ability to work with multi-million gate designs
- Ability to solve problems using a systematic approach
Preferred qualifications:
- Demonstrated strong analytical and problem-solving skills
- Strong verbal and written communication skills
- Ability to work in teams and collaborate effectively with people in different functions
- Strong time management skills that enable on-time project delivery
- Demonstrated ability to build strong, influential relationships
- Ability to work effectively in a fast-paced and rapidly changing environment
- Ability to take the initiative and drive for results