Change the world. Love your job.
In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.

Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.

As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.

This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.

Minimum requirements:

• 5 years of relevant experience
• A thorough understanding of digital logic design
• Familiarity with the Verilog language and simulators
• A good understanding of analog functionality and exposure to analog IC design methods
• Ability to solve problems using a systematic approach

Preferred qualifications:

• Experience with System Verilog
• Demonstrated strong analytical and problem solving skills
• Strong verbal and written communication skills
• Ability to work in teams and collaborate effectively with people in different functions
• Strong time management skills that enable on-time project delivery
• Demonstrated ability to build strong, influential relationships
• Ability to work effectively in a fast-paced and rapidly changing environment
• Ability to take the initiative and drive for results

Responsibilities

• Own complete RTL2GDSii flow implementation including timing and Reliability Signoff of complex Power Managed subchips – synthesis, PnR, timing closure and power grid closure to meet PPA goals
• Understand the design, clock architecture, reset architecture, DFT architecture and interface with FE/IP teams to influence architecture decisions as per Physical Design needs.
• Responsible for low-power implementation at IP/subsystem/SoC level including CLP/LEC checks
• Own development of constraints for Synthesis and STA for complex subchips
• Implement methodologies to keep the PD cycle efficient and predictable.
• Implement Techniques to reduce Power and Area to make the device competitive

Qualifications

• 3-8 years’ experience working on IP/subsystem/SoC Physical Design activities with a Bachelor or Master’s degree in EE/ECE/CS or related specializations

Skills

• Strong experience in one or more of the following – Synthesis, PnR, STA for a complex, high speed IP/subsystem
• Good working knowledge of constraints, timing closure basics and Clock tree synthesis is a must
• Working knowledge in advanced low power techniques and tools such as UPF/CPF/CLP and power aware implementation
• Good understanding and mastery in PD flow using Cadence tools like Genus, Innovus and Tempus
• Working knowledge of Reliability concepts like ESD, Latchup, IR drop etc is a definite plus
• Good understanding of SoC Debug architectures, Design-for-Debug, Design-for-Test
• Excellent debugging and problem solving skills
• Effective communication skills to interact with all stakeholders
• Must be highly focused and remain committed to obtaining closure on project goals