DFM Engineer

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A Process Development Engineer is responsible for the development, characterization and optimization of MEMS resonator devices to meet the requirements for volume production as part of the analog technology development team. The ideal candidate will be a technical leader in the area of resonators and oscillators driving the characterization and optimization of the device and process to insure robustness, reliability, and manufacturability meeting all electrical device performance targets.

We are seeking a highly skilled and motivated OPC/DFM Engineer to join our RET (Resolution Enhancement Techniques) team in Advanced Technology Development (ATD). The successful candidate will be responsible for developing, optimizing, and deploying Optical Proximity Correction (OPC) and Design for Manufacturability (DFM) solutions to ensure high-yield, high-performance semiconductor products. This role requires a strong understanding of lithography, RET (Resolution Enhancement Technology), layout design, and process integration. You will collaborate with layout, process, and lithography teams to optimize design rules and enable robust tapeouts.

Responsibilities:

• Develop, evaluate, and implement advanced OPC models and recipes for various technology nodes.
• Perform comprehensive DFM analysis on designs, identifying and mitigating potential manufacturing issues (e.g., hot spots, yield detractors).
• Collaborate closely with design teams to provide DFM guidelines and ensure design compliance with manufacturing capabilities.
• Work with lithography and process engineering teams to optimize OPC recipes and improve patterning performance, yield, and process window.
• Interface with OPC and lithography engineers to co-optimize layout structures for printability
• Analyze lithography process data and wafer yield data to identify root causes of patterning defects and implement corrective actions.
• Evaluate and qualify new OPC/DFM software tools and methodologies.
• Develop and maintain automation scripts for OPC/DFM flows.
• Stay abreast of industry trends and advancements in lithography, OPC, and DFM.
• Document best practices, methodologies, and engineering solutions.
• Mentor junior engineers and contribute to knowledge sharing within the team.
• Contribute to development of DFM-aware layout methodologies for custom analog IPs.

Minimum requirements:

• Master's in Electrical Engineering, Physics, Materials Science, or a related field.
• 5+ years of experience in OPC and DFM in the semiconductor industry.
• Strong understanding of optical lithography principles, RET (e.g., OPC, SRA, assist features), and mask technology.
• Hands-on experience with industry-standard OPC software tools (e.g., Synopsis Sentaurus Lithography, Mentor Calibre, ASML Brion).
• Proficiency in scripting languages such as Python, TCL, Perl, or similar.
• Familiarity with 28nm/22nm process limitations and lithographic constraints.
• Experience in analog layout interaction with lithography and OPC flows.

Preferred Qualifications:

• PhD in Electrical Engineering, Physics, Materials Science, or a related field.
• Experience with advanced technology nodes (e.g., 45nm, 28nm, 22nm, and 20nm).
• Solid knowledge of semiconductor device physics and fabrication processes.
• Experience with statistical data analysis and yield improvement methodologies.
• Ability to work effectively in a cross-functional team environment.
• Excellent problem-solving, analytical, and communication skills.
• Familiarity with layout design tools (e.g., Cadence Virtuoso).
• Knowledge of design rule checking (DRC) and layout versus schematic (LVS).
• Experience with machine learning or AI techniques applied to OPC/DFM.