Senior Design Verification Engineer
TalentLab Inc
Senior Design Verification Engineer
Our client is a key player in advancing digital technology by accelerating high-performance data communication—from AI and the metaverse to seamless video and beyond. Their technology is foundational to innovation across data-heavy industries such as data centers, AI, networking, storage, 5G, and autonomous vehicles. Known for their cutting-edge solutions and reliable execution, they help shape the future of digital systems.
The Digital Design Verification team fosters a collaborative, growth-oriented culture where engineers are encouraged to take on new challenges, learn continuously, and contribute to impactful projects. This group is dynamic, supportive, and a great fit for professionals looking to build their career in semiconductors.
What You’ll Do
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Review design specifications and develop robust verification plans.
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Build testbenches, run simulations, and debug failures to uncover design bugs.
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Take initiative in leading, planning, and coordinating verification tasks with team members.
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Create behavioral models of analog circuits.
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Support bit-matching between RTL designs and MATLAB system models.
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Integrate third-party VIPs for compliance testing of standard protocols.
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Prepare design IP releases for customer delivery.
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Collaborate in post-silicon validation and bring-up efforts.
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Work closely with cross-functional teams—including Design, Systems, Analog, Firmware, and PD—to ensure final verification closure.
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Continuously improve verification methodologies, tools, and team processes.
What You’ll Need
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3 to 8 years of relevant experience in design verification.
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Strong skills in SystemVerilog and UVM for constrained-random verification.
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Experience verifying SerDes PHYs, DSPs, and mixed-signal analog designs.
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Knowledge of Ethernet and PCIe protocols is highly desirable.
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Familiarity with formal verification and power-aware UPF verification techniques.
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Proficiency in SystemVerilog, UVM, Python, Perl, C/C++, and GNU Make.