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Analog IC Design Engineer

TalentLab Inc

TalentLab Inc

Design
Toronto, ON, Canada
Posted on Apr 9, 2025

Analog IC Design Engineer

Our client, a leader in advanced connectivity solutions, is shaping the future of high-speed data communication—powering innovation across AI, data centers, 5G infrastructure, autonomous vehicles, and beyond. As part of their Connectivity Products Group, you’ll help drive the development of next-generation direct detect and Coherent DSP solutions enabling 800Gbps, 1.6Tbps, and higher-speed interconnects.

As an Analog IC Design Engineer, you’ll contribute to cutting-edge analog and mixed-signal circuit design from concept through silicon characterization, collaborating with an elite team to push performance and power boundaries across advanced CMOS nodes.

What You’ll Do

  • Design and verify high-performance analog blocks aligned with system and industry specifications.

  • Collaborate with a team of top-tier engineers—supporting and being supported through shared ownership and technical leadership.

  • Optimize circuits to meet power, performance, and area (PPA) goals.

  • Propose and implement design and verification strategies to ensure robust, silicon-proven circuits.

  • Guide and review physical layout to reduce parasitics, stress, and process variability.

  • Present simulation results for peer review and technical validation.

  • Document design features, testbench setups, and key performance indicators.

  • Support the characterization team to validate post-silicon performance and correlate measurements to simulations.

What You’ll Need

  • MSc or PhD in Electrical Engineering, Engineering Science, or a related technical field.

  • 5+ years of experience in analog IC design, preferably with silicon-proven results.

  • Hands-on experience with advanced CMOS nodes.

  • Design experience with any of the following blocks: CTLE, slicers, high-speed ADCs, VCOs, PIs, PLLs, bandgaps, regulators, serializers/deserializers, phase detectors, or high-speed TX/RX architectures.

  • Strong understanding of parasitic-aware layout and reliability considerations (aging, stress, EM).

  • Proficiency with EDA tools for schematic, layout, and verification workflows.

  • Solid simulation background, including SPICE and behavioral modeling using Verilog-A.

Location: Toronto – reporting to the Senior Director, Connectivity Products Group.

Please reach out to nick.weiszhaar@talentlab.com with your resume if you're a fit for the position and interested in learning more.