Category Engineering Hire Type Employee Job ID 10862 Remote Eligible No Date Posted 13/07/2025

Job Titles:

• Senior Staff ASIC RTL Design Engineer - Bangalore location

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and highly skilled digital design engineer with a strong background in ASIC RTL design. You thrive on technical challenges, enjoy collaborating with global teams, and are motivated by seeing your designs come to life in real-world products. With over8 years of hands-on experience in architecting, implementing, and verifying complex digital systems, you are adept at translating functional specifications into efficient, robust RTL. Your experience spans data path and control path designs, and you are comfortable working with industry-standard protocols such as Ethernet, DDR, PCIe, USB, and AMBA.You possess deep expertise in synthesizable Verilog/SystemVerilog, design flows, and EDA tools. You are equally at home mentoring junior engineers as you are diving deep into code or debugging complex issues. Your ability to balance area, latency, and throughput trade-offs sets you apart, and your attention to detail ensures high-quality, reliable IP cores. You communicate effectively with both technical and non-technical stakeholders and are comfortable engaging with customers to clarify requirements and ensure successful delivery.You value diversity, inclusion, and continuous learning, and you bring a collaborative spirit to every project. If you’re ready to lead, innovate, and make a tangible impact in the world of high-performance silicon design, Synopsys is the place for you.

What You’ll Be Doing:

• Architecting, designing, and implementing state-of-the-art RTL for high-performance synthesizable IP cores within the DesignWare family.
• Translating complex functional and standard specifications into detailed architecture and micro-architecture documents for medium to high complexity blocks.
• Owning the entire digital design lifecycle, including RTL coding, synthesis, CDC analysis, debugging, and test development.
• Collaborating with global, multi-site teams of expert engineers to drive technical excellence and innovation.
• Interacting with customers to understand and refine specification requirements and providing technical guidance as needed.
• Mentoring and technically leading junior designers, fostering growth and sharing best practices within the team.
• Participating in design reviews, quality process improvements, and ensuring adherence to industry-leading verification and design methodologies.

The Impact You Will Have:

• Delivering robust, high-quality IP cores that power next-generation commercial, enterprise, and automotive applications worldwide.
• Driving innovation in digital ASIC design, enabling faster, more efficient, and reliable silicon solutions for Synopsys customers.
• Contributing to the advancement of industry standards and protocols through technical leadership and deep domain expertise.
• Enhancing team performance through mentorship, knowledge sharing, and technical guidance.
• Strengthening Synopsys’ reputation as a leader in chip design by consistently delivering on complex customer requirements.
• Accelerating product development cycles by streamlining design processes and championing best-in-class methodologies.

What You’ll Need:

• Bachelor’s or Master’s degree in EE, EC, or VLSI with8+ years of relevant industry experience in digital ASIC RTL design.
• Expertise in data path and algorithmic block design (e.g., Reed Solomon FEC, BCH codes, MAC SEC engines) and architecture trade-offs.
• Proficiency in synthesizable Verilog/SystemVerilog RTL coding, simulation, and EDA tools.
• Hands-on experience with design flows including Lint, CDC, synthesis, static timing analysis, and formal checking.
• Strong knowledge of industry-standard protocols (Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA AXI/AMBA2).
• Experience with high-speed design (>600MHz), P&R aware synthesis, and tools like Fusion Compiler is a significant plus.
• Familiarity with revision control systems (e.g., Perforce) and scripting languages (Perl/Shell).
• Prior experience as a technical lead or mentor within a design team is highly desirable.

Who You Are:

• A collaborative team player who thrives in a global, distributed environment.
• An effective communicator, adept at conveying complex technical ideas to diverse stakeholders.
• A proactive problem-solver with strong analytical skills and high initiative.
• Detail-oriented, quality-focused, and committed to delivering excellence.
• Passionate about mentoring and enabling the growth of others.
• Dedicated to diversity, inclusion, and fostering an open, respectful workplace.

The Team You’ll Be A Part Of:

You’ll be an integral member of the DesignWare IP Design R&D team at Synopsys Bangalore, collaborating with some of the brightest minds in the industry. The team is focused on developing cutting-edge synthesizable IP cores that are deployed in a wide range of commercial, enterprise, and automotive applications. Working in a multi-site, global environment, you’ll have opportunities to engage with cross-functional teams, contribute to technical excellence, and drive innovation in digital design.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.