We are looking for an intern like you to be part of the team to work on verification project release

Job Description:

• To develop and execute verification tasks with architects, design and verification teams.

Job Requirements:

• Understanding of design/verification languages such as, SystemVerilog, Verilog
• Understanding of Coverage Driven Verification, constrained random testing
• Familiarity with SystemVerilog, UVM is a plus
• Knowledge of tools such as, RTL Simulators, e.g. VCS, Verdi
• Knowledge of HDL design and ideally, RISC architectures, multi-core, etc.
• Excellent written and verbal skills including: Written and spoken English, Detailed status reporting;
• The minimum contract term should be 6 months
• A Bachelor’s degree in engineering is a minimum requirement
• Working in the office in Wuhan

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.