We are looking for a Senior Staff Interposer Design Engineer to join our team. Ensuring Synopsys IP test chip packages meet performance requirements and helping customers explore their advanced package solution space options with Synopsys IPs. Candidate with package design and model extraction experience required. Can-do attitude, quick learning, and solid electronic skills are assets. You will be working with a global, highly skilled and very supportive team.

Responsibilities

•Early design stage collaboration to optimize and define requirements for SIPI performance (e.g., bump maps, power estimation)

•Responsible for advanced package designs, such as silicon interposers, RDL fanout packages and silicon bridge packages

•Models, and analyze advanced package designs

•Represents the organization on business unit projects

•Resolves a wide range of issues in creative way regularly

Requirements

•Bachelor’s degree in electrical or Electronic Engineering

•Minimum of 10 year of relevant experience

•Advanced circuit and transmission line theory knowledge

•Knowledge of advanced package technology and hands on experience with TSMC/Intel/Samsung/OSAT advanced package designs preferred

•Experience with 3DIC packaging and multi-physics analysis (EMIR, Thermal, Thermal-Mechanical, Electromagnetic, etc.) is a plus

•Familiarity with both Windows and Linux operating systems

•Tools experience with Cadence APD, Innovus, Integrity-3DIC; Synopsys ICC2, 3DIC Compiler, Fusion Compiler is beneficial

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.