Job Description for -ASIC Digital Design Engineer, Architect

We have multiple openings for senior positions both at design and verification . We are looking for design and verification experts to work on implementation of design and verification of RTL based IP cores implementing complex protocols. The candidate (design/verification) will be part of the Solutions Group at our Bangalore Design Center, India and will be responsible for RTL design / functional verification solutions for the IP which is used in end-customer applications such as server farms, AI/machine learning, automotive, etc. The candidate will work with our internationally based team of architects/designers/other verification team members across multiple sites worldwide. The position offers learning and growth opportunities. This is a Senior Technical Individual Contributor role and offers challenges to work on technically challenging IP Cores.

Job responsibilities and Key Qualifications for RTL Design

Job Responsibilities --
* Understand Standards / functional specifications for the product and write architecture / microarchitecture specifications
* Make architecture decisions on the design
* Implement RTL design and basic verification
* Work with the verification team to define the verification requirements
* Perform technical lead role

Key Qualifications --

Must have BSEE in EE or MSEE with 20+ years of experience in the following areas:
* Knowledge of one or more of protocols DDR/PCIE/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/ Ethernet/ USB/ MIPI
* Hands on experience with creating micro-architecture/ detailed design from Functional Specifications
* Hands on experience with Verilog/ System Verilog coding and Simulation tools
* Synthesis flow and static timing flows, Lint, CDC, Formal checking
* Prior experience with SVA and formal verification tools is an added advantage
* Knowledge of C/C++, TCL, Perl, Python is an added advantage
* Ability to work independently, precisely and to drive innovation
* Ability to extract detailed product requirements from high-level specification
* Good communication skills.
* Experience of working with Functional safety, ISO26262 , FMEDA is an added advantage

Job Responsibilities and Key Qualifications for Functional Verification

Job Responsibilities --

* Make architecture decisions on test bench design
* Write verification plans and specifications
* Implement test bench infrastructure and write test cases
* Implement a coverage driven methodology

* Perform technical lead role

Key Qualifications --

* Make architecture decisions on test bench design
* Write verification plans and specifications
* Implement test bench infrastructure and write test cases
* Implement a coverage driven methodology

* Perform technical lead role


Must have BSEE in EE with 20+ years of relevant experience or MSEE with 18+ years of relevant experience in the following areas:
* Knowledge of one or more of protocols: DDR/PCIE/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/ Ethernet/USB/ MIPI
* Hands on experience in creating Test Environment from Functional Specifications using UVM/VMM/OVM, Test Planning, Coverage closure, Assertion based verifications
* Proficient in SV and UVM, Object oriented coding and verification
* Able to provide verification solutions for productivity, performance and throughput improvement
* Knowledge of C/C++, TCL, Perl, Python is added advantage
* Ability to work independently, precisely and to drive innovation
* In addition, the candidate should have good communication skills, will be a team player and will have good problem solving skills.
* Experience of working with Functional safety, ISO26262 , FMEDA is an added advantage

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.