We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled and experienced ASIC Digital Design Engineer with a passion for innovation and problem-solving. With a Bachelor's degree and 8-9 years of related experience or a Master's degree with 6-7 years of related experience, you have honed your expertise in frontend design, integration, synthesis, and chip-level verification. Your proficiency in Verilog coding and testbench creation is complemented by your ability to work independently, debug complex issues creatively, and suggest improvements to design and verification methodologies.

You are an excellent communicator, capable of effectively engaging with team members and external parties. Your knowledge of scripting languages such as Perl, Python, and Tcl enhances your ability to streamline processes and optimize performance. As a mentor, you coach and guide junior engineers, fostering a collaborative and innovative environment.

What You’ll Be Doing:

• Defining and developing ASIC RTL designs and verification at both chip and block levels.
• Integrating and synthesizing complex ASIC designs.
• Creating and maintaining testbenches to verify design functionality.
• Debugging and resolving complex design issues independently and effectively.
• Suggesting and implementing improvements to design and verification methodologies.
• Collaborating with cross-functional teams to ensure seamless integration and functionality.

The Impact You Will Have:

• Driving the development of high-performance ASIC designs that meet industry standards.
• Ensuring the reliability and functionality of designs through rigorous verification processes.
• Contributing to the continuous improvement of design and verification methodologies.
• Mentoring and guiding junior engineers, fostering a culture of innovation and excellence.
• Enhancing the overall efficiency and performance of the design process through scripting and automation.
• Supporting the successful delivery of cutting-edge technology solutions to market.

What You’ll Need:

• Bachelor’s degree with 8-9 years of related experience or a Master's degree with 6-7 years of related experience.
• Extensive experience in frontend design, integration, synthesis, and chip-level verification.
• Expertise in Verilog coding and testbench creation.
• Strong problem-solving skills with the ability to debug and resolve complex issues.
• Proficiency in scripting languages such as Perl, Python, and Tcl.

Who You Are:

• Excellent communicator with the ability to engage effectively with internal and external stakeholders.
• Independent and self-motivated, capable of working with limited supervision.
• Creative problem-solver with a keen eye for detail.
• Collaborative team player who fosters a positive and innovative work environment.
• Mentor and coach to junior engineers, guiding their professional growth.

The Team You’ll Be A Part Of:

You will be part of a dynamic and innovative team focused on ASIC digital design and verification. Our team is dedicated to pushing the boundaries of technology, delivering high-performance solutions, and continuously improving our methodologies. Collaboration and knowledge-sharing are at the core of our success, and we thrive on solving complex challenges together.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.