We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned professional with a passion for exploring new technologies and solving complex problems. With a minimum of 5+ years of related experience, you possess a comprehensive understanding of ASIC Physical Design and a working knowledge of multiple related areas. You are adept at using tools like DC, ICC2, StarRC, and PT-SI, and have a strong desire to continue learning and growing in your field. You thrive in both independent and collaborative work environments, frequently interacting with senior internal and external personnel to achieve project goals. Your excellent communication skills and ability to work as part of a team are crucial, as you will be engaging in daily technical interactions with both local and US counterparts. Experience in DDR power signoff and the ability to handle challenges such as timing closure above ~2GHz, mixed signal macro IP integration, and building efficient clock trees with tight skew balancing are highly valued.

What You’ll Be Doing:

• Implementing and power signoff of world-class DDRs at cutting-edge technology nodes.
• Achieving timing closure above ~2GHz and integrating mixed signal macro IPs.
• Building efficient clock trees with very tight skew balancing.
• Providing regular updates to your manager on project status.
• Guiding junior peers with aspects of their job and contributing to their development.
• Representing the organization on business unit and/or company-wide projects.

The Impact You Will Have:

• Driving the implementation of cutting-edge DDR technology, contributing to the advancement of high-performance computing.
• Ensuring the power efficiency and performance of our silicon chips, crucial for our competitive edge.
• Enhancing the reliability and integration of mixed signal macro IPs.
• Contributing to the overall success and innovation of Synopsys' IP solutions.
• Mentoring junior engineers, fostering a culture of continuous learning and improvement.
• Representing Synopsys in key projects, influencing the direction and success of our initiatives.

What You’ll Need:

• Minimum of 5+ years of related experience in ASIC Physical Design.
• Proficiency in tools like DC, ICC2, StarRC, and PT-SI.
• Strong understanding of timing closure, power signoff, and mixed signal macro IP integration.
• Experience with DDR power signoff and clock tree building.
• Excellent problem-solving and analytical skills.

Who You Are:

• A strong team player with excellent communication skills.
• Independent and collaborative, capable of working with minimal supervision.
• Creative and innovative, able to develop unique solutions to complex problems.
• Detail-oriented and organized, ensuring high-quality project outcomes.
• Passionate about continuous learning and professional growth.

The Team You’ll Be A Part Of:

You will be part of the SNPS DDR/HBM/UCIe/Die-to-Die IP implementation team, focusing on the implementation and power signoff of world-class DDRs. This team is dedicated to pushing the boundaries of technology and delivering high-performance solutions that drive the future of computing.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.