Synopsys is looking for Senior Layout Design Engineer to work on next generation of PLLs for world leading system-on-chip (SOCs) in leading edge CMOS technology nodes!

This position targets Engineers for layout design of integrated, high-performance, high-speed analog circuits.

The core focus of the work will be on design of Phase Lock Loops, Delay Locked Loops, Phase mixers and custom digital blocks used in SERDES interfaces.

The candidate will be part of design team and will closely collaborate on delivering best in class in terms of Power, Performance and Area Ring Oscillator PLLs which will be used in Synopsys consumer SERDES PHYs.

Key Qualifications:

University degree in Electronics/Engineering

Good understanding CMOS technologies.

Working experience with electronics or PCB design

Familiarity with UNIX operating systems.

Ability to build relations and keep teamworking.

Good written and verbal communication skills in English and Polish and problem-solving skills.

Organizational skills are essential.

Experience in CMOS analog and mixed-signal layout design is welcome.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.