We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a dedicated and innovative engineer with a passion for analog design. With a strong background in CMOS processes and deep submicron technologies, you are adept at tackling complex design challenges. You bring at least 1 year of experience in CMOS circuit design and layout methodology, and have a basic understanding of Analog/mixed signal circuitry. Your familiarity with JEDEC requirements for DDR interfaces, DDR Timing, ODT, and SDRAM functionality gives you an edge in designing cutting-edge solutions. You thrive in a collaborative environment, communicating effectively with internal development teams, and are committed to delivering high-quality designs efficiently. Your enthusiasm for continuous learning and improvement drives you to stay updated with the latest industry trends and advancements.

What You’ll Be Doing:

- Designing DDR I/O circuits to meet stringent performance and reliability standards. - Collaborating with cross-functional teams to integrate analog designs into SoCs. - Performing circuit simulations and validating design performance. - Ensuring compliance with JEDEC standards for DDR interfaces. - Contributing to layout design and methodology improvements. - Troubleshooting and resolving design issues to optimize product quality and efficiency.

The Impact You Will Have:

- Enhancing the performance and reliability of our silicon IP products. - Accelerating the integration of advanced capabilities into SoCs. - Reducing time-to-market for differentiated products. - Minimizing design risks and ensuring compliance with industry standards. - Driving innovation in analog design methodologies. - Supporting the development of cutting-edge technologies that power the Era of Smart Everything.

What You’ll Need:

- BTech/MTech in Electrical Engineering or related field 1-3years of experience in CMOS circuit design and layout. - Knowledge of deep submicron process technologies. - Familiarity with JEDEC standards for DDR interfaces. - Basic understanding of analog/mixed signal circuitry and ESD concepts.

Who You Are:

- A collaborative team player with strong communication skills. - Detail-oriented and committed to delivering high-quality designs. - Innovative and eager to tackle complex design challenges. - Adaptable and open to continuous learning and improvement. - Passionate about technology and its potential to transform industries.

The Team You’ll Be A Part Of:

You will join our Silicon IP team, which focuses on integrating advanced capabilities into SoCs to meet unique performance, power, and size requirements. Our team works collaboratively to push the boundaries of technology, delivering a broad portfolio of silicon IP that powers the next generation of smart devices.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.