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FPGA/RTL Design Engineer (R&D Engineering, Sr Staff Engineer)

Synopsys

Synopsys

Design
Bengaluru, Karnataka, India
Posted on Feb 25, 2025

We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

What You’ll Be Doing:

  • Create Functional Specifications for IP modules
  • Define Microarchitecture, develop RTL code and handle timing closure
  • Develop application scripts to control designs from host machines
  • Bring up of design on hardware systems
  • Create and execute hardware validation test suites to ensure highest quality and reliability
  • Enhance and maintain existing product and features
  • Innovate and think out-of-the box to push the envelope on IP performance and area

What You’ll Need:

  • BE/BTECH with 12yrs of experience, Master's with 10+yrs of experience
  • Experience in designing for Xilinx and Altera FPGA’s.
  • Experience in strategically using third-party IPs from Xilinx/Altera IP catalogs
  • Exposure to tools like Xilinx Vivado, IP integrator, Vitis, Altera Quartus II etc.
  • Experience in RTL development using Verilog, system Verilog
  • Experience in designing with SerDes IP
  • Experience in design of standard protocol IPs like USB, PCIe, DDR, AXI is
  • Experience in emulation/prototyping is a plus
  • Experience in using Lint, CDC checker tools
  • Experience in full design flow including verification and lab bring up.
  • Hands-on experience using scripting languages like Tcl, Python, Perl etc.
  • Currently pursuing a bachelor’s degree in electronic engineering, Computer Science, or a related field in the penultimate year of study
  • Strong understanding of digital design, complex IP microarchitecture, multi-clock domain synchronization, and static timing analysis
  • Understanding of FPGA Architecture and complete flow
  • Skills needed for bring-up and debug of FPGA hardware
  • Ability to handle complex technical assignments independently
  • Exhibit strong work ethics and collaborative spirit