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Come and be part of a collaborative team environment that innovates and develops the latest IP solutions that enable the way the world designs. Join US! Senior ASIC Design Engineer
You would be working as part of a highly experienced mixed-signal design team, targeting the next generation PAM-based SerDes products. Strong theoretical and practical background in high-speed serializer and data recovery circuits is an asset. The position offers an excellent opportunity to work with an experienced team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on the test-chips. Qualifications
Must have hands-on experience in RTL design(Verilog or System Verilog)
Must have hands-on experience with multiple clock domain design
Have experience with CDC/RDC/LINT tools
Have experience in defining synthesis constraints and STA
Good understanding of digital signal processing
Good organization and communication skills for interacting between different design groups and customer support teams
Knowledge of the following will be considered as an important asset:
High-speed digital & mixed-signal design
Experience in analog design
DFT design methodologies |
