We are looking for highly motivated experienced ASIC Digital Design Engineer to be part of High Speed Serdes Digital Design Team. As part of this team , you will be working on digital part of serial link PHY IPs covering USB , PCIe Display & HDMI standards.

Job Description:

• Drive and work on digital design for High speed serial Interface PHY IPs for USBx, PCIex, Ethernet, Display & HDMI protocol standards.
• Propose micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements , Link layer i/f changes or overall robustness of design
• Implement RTL in Verilog and run Spyglass CDC/RDC/Lint
• Work with verification to test the desired functionality & corner cases
• Develop timing constraints , DFT insertion , Test coverage & close timing with Physical Design teams
• Support validation and characterization through Test chip development or FPGA based prototyping

Requirements

• Experienced digital FE designer with 5 - 8 years of relevant experience
• Digital design sound hold of ASIC digital design flow with experience in below domains
• Verilog RTL design
• Timing constraints development and synthesis flow
• Lint/CDC/RDC using Spyglass or any other tool
• Scripting and automation using TCL/PERL/Python
• Excellent debug skills

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.