Senior ASIC Design Engineer

You would be working as part of a highly experienced digital design team, targeting the next generation ARC processor IP. The ideal candidate is experienced in microprocessor development process and resolution of critical problems. The position offers an excellent opportunity to work with an experienced team of engineers involved in defining and implementing Functional Safety for all ARC Processor IPs.

Key Qualifications

• MSEE graduate plus minimum 3+ years or BSEE graduate plus minimum 5+ years of digital design experience in the industry
• Must have hands-on experience in RTL design (Verilog or System Verilog). Familiarity with Computer architecture concepts
• Must have experience with CDC/RDC/LINT tools
• Hands-on expertise with debugging failed scenarios using DVE/Verdi
• Scripting experience in one or more languages: Shell, Perl, Python
• Good organization and communication skills for interacting between different design groups
• Must be self-motivated, proactive, and able to balance good design quality while meeting tight deadlines

Preferred Qualifications / Skills

• Hands-on experience with multiple clock domain design
• Scripting experience in Shell, Perl, Python and TCL is a plus
• Familiarity with Trace/Debug is highly desirable (Nexus, Coresight)

• RISC-V experience highly desirable
• Excellent problem-solving skills
• Experience with GIT or other revision control environments

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.