Principal Verification Design Engineer
Synopsys
Design
Sunnyvale, CA, USA
Posted on Dec 17, 2024
Category Engineering Hire Type Employee Job ID 8305 Base Salary Range $177000-$265000 Remote Eligible No Date Posted 15/12/2024
| We Are: |
| At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. |
| You Are: |
| You are a passionate and detail-oriented Verification Design Engineer with a deep understanding of PHY verification strategy and test plans. You thrive in dynamic environments and have a strong background in analog mixed signal verification, firmware, and ensuring PHY quality. You are adept at coaching and enabling teams, particularly in the domain of Verification and Validation (VN). Your expertise in ASIC Digital Design and verification at both chip and block levels sets you apart, and you are eager to leverage your skills to drive innovation at Synopsys. |
| With a proactive attitude, you excel in planning, developing, and executing verification strategies. Your excellent communication skills allow you to articulate complex technical concepts to diverse audiences, fostering collaboration and driving successful project outcomes. You are committed to continuous learning and staying abreast of the latest advancements in verification and design methodologies. |
| What You’ll Be Doing: |
| Collaborating with cross-functional and cross-geo teams to define and implement best in class Die to Die IP design at PHY and controller levels. |
| Develop and implement PHY verification strategies and comprehensive test plans. |
| Review and refine test plans to ensure alignment with project goals and industry standards. |
| Implement PHY and controller testbenches, monitors and scoreboards using UVM methodology |
| Achieve code coverage goals and ensure thoroughly verified designs |
| Work with the Lab/System team for test plan, silicon bring up and debug |
| Conduct Analog Mixed Signal Verification and Validation (VAL) for high-quality Die to Die IP |
| Collaborate with firmware teams to integrate and test firmware components. |
| Ensure the highest standards of Die to Die PHY quality through rigorous testing and validation processes. |
| Coach and enable the global Verification and Validation (VN) team to achieve optimal performance. |
| The Impact You Will Have: |
| Driving the quality of world class high-performance D2D IPs to enable customer chiplet bases system design win across industries |
| Drive the development of cutting-edge verification strategies that enhance product reliability. |
| Ensure the delivery of high-quality PHY components that meet industry standards. |
| Contribute to the overall success of Die to Die IP Design projects through meticulous verification. |
| Enhance collaboration between analog, RTL, controller, firmware, and SOC design teams. |
| Elevate the capabilities of the global verification team through effective coaching and mentorship. |
| Play a pivotal role in advancing Synopsys' leadership in semiconductor design and verification. |
| What You’ll Need: |
| Significant Experience with coding in System Verilog or Verilog and UVM methodology |
| Experience in verification of DDR/HBM memory or Die to Die interfaces is higly desirable |
| Significant Experience with standard IP/SOC Verification flow/software tools |
| Strong knowledge of scripting, Linux/Unix environment |
| Experience in testplan review and analog mixed-signal verification. |
| Expertise in ensuring PHY quality through rigorous testing. |
| Ability to coach and enable verification teams. |
| Experience in leading and driving technical solutions across organization |
| The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams |
| Who You Are: |
| A proactive and detail-oriented engineer. |
| An effective communicator with strong interpersonal skills. |
| A collaborative team player who thrives in dynamic environments. |
| A dedicated mentor committed to the development of others. |
| A continuous learner passionate about staying current with industry advancements. |
| The Team You’ll Be A Part Of: |
| You will join a dedicated and innovative team focused on ASIC Digital Design and verification. Our team collaborates closely with firmware, design, and verification experts to deliver high-performance silicon chips. We value open communication, continuous improvement, and a commitment to excellence in all our projects. |
| Rewards and Benefits: |
| We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. |
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.