Analog Design, Principal Engineer/SerDes
Synopsys
Design
Pavia, Province of Pavia, Italy
Posted on Dec 17, 2024
Category Engineering Hire Type Employee Job ID 4573 Remote Eligible No Date Posted 23/08/2024
We're looking for an Analog Design Engineer, Principal to join our team. Does this sound like a good role for you?
In this role, you will work on the design, development, and refinement of Multi-Gbps PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team, developing high speed analog integrated circuits in the latest FinFET process nodes. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
Main Responsibilities:
In this role, you will work on the design, development, and refinement of Multi-Gbps PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team, developing high speed analog integrated circuits in the latest FinFET process nodes. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
Main Responsibilities:
- Investigate and contribute developing circuit architectures that address architectural bottlenecks and drive to revolutionary improvements in power, area and performance targets.
- Drive macro-blocks definition, design and implementation
- Document design features and test plans.
- Consult on the overall electrical characterization of the SerDes IP product. Investigate customer silicon data for design enhancements. Propose solutions for post-silicon design updates.
Key Requirements:
- PhD, or MSc with 15+ years of practical analog IC design experience. Degree in Electrical Engineering or similar field.
- Deep knowledge of transistor level circuit design, with particular focus on high-speed analog design
- Solid design experience with SerDes system and blocks, like: receive equalizers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC
Experience in the following aspects of the design process is considered as a plus:
- Expertise of layout effects (i.e. matching, reliability, proximity effects, etc.).
- Knowledgeable in Verilog-A for analog behavioral modeling
- Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is a nice to have.
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP: predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.