• Bachelor’s degree in engineering is required as a minimum from a reputed college
• Minimum eight years of experience in digital front end functional verification
• Microprocessor architecture knowledge
• HDL and Verification languages: SystemVerilog, Verilog
• Verification methodologies: UVM/OVM
• Programming skills: C, assembly, Perl, makefile generation
• Tools: RTL Simulators, eg VCS.
• Experience in technical leadership of a verification team
• Experience in working with global teams
• Written and Verbal communication skills:
  • Creation, modification and review of test documentation: testplans, procedures, test scenarios, test reports
  • Ability to represent verification team in global platforms
• Analytical skills:
  • Analysis of verification requirements to close out on product release
  • Ability to analyze test results and provide reports
  • Provide guidance to team based on result analysis
• Self-motivated team player able to thrive in a fast-paced engineering environment
• Inspire team for technical excellence

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.