Senior ASIC Physical Design Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

An experienced and passionate ASIC Physical Design Engineer ready to take on new challenges in advanced technology nodes. You thrive in dynamic environments and are adept at working collaboratively with cross-functional teams. Your strong technical background in Place and Route, Physical Verification, and ASIC design flow equips you to tackle complex problems and deliver high-quality solutions. Your communication skills enable you to effectively interact with different functional teams and support customer queries and issues. You are committed to continuous learning and staying updated with the latest industry trends and technologies.

What You’ll Be Doing:

• Developing robust ASIC design flows to build and verify standard cell libraries for optimal PPA.
• Executing Place and Route using ICC-II/FC tools.
• Interacting with logic library organizations and tools teams to report and resolve issues identified during library validation.
• Collaborating with the Application Engineering team to address customer queries and issues.
• Ensuring all stages of the ASIC design flow, including Synthesis, Timing Analysis, Floor Planning, Power Planning, CTS, ECO Flow, STA, Power Analysis, Timing, and Design Closure, are meticulously executed.
• Applying low power concepts and working with UPF/CPF formats.

The Impact You Will Have:

• Enabling the integration of advanced capabilities into SoCs, meeting unique performance, power, and size requirements.
• Accelerating time-to-market for differentiated products with reduced risk.
• Enhancing the quality and reliability of standard cell libraries through meticulous validation processes.
• Supporting the development and optimization of cutting-edge technologies for chip design and software security.
• Contributing to Synopsys' leadership in the semiconductor industry by delivering high-performance silicon solutions.
• Driving innovation in the Era of Smart Everything, impacting everyday technologies like self-driving cars, AI, and 5G.

What You’ll Need:

• Bachelor’s or Master’s degree in Electronics or Electrical Engineering or equivalent from reputed universities.
• 4-6 years of experience in ASIC Physical Design.
• Experience with advanced technology nodes such as 28nm, 16nm, 14nm, 10nm, and 7nm.
• Strong understanding of CMOS logic design at both gate and circuit levels.
• Proficiency in Place & Route and Physical Verification (DRC/LVS).
• Familiarity with all stages of the ASIC design flow, including Synthesis, Timing Analysis, Floor Planning, Power Planning, CTS, ECO Flow, STA, Power Analysis, Timing, and Design Closure.
• Knowledge of low power concepts and UPF/CPF formats.
• Understanding of Technology files, Liberty, Lef, Def, Gds, and standard cells view generation processes.
• Experience using Synopsys tools like ICC-II, FC, DC, PT, and ICV. Knowledge of Cadence and Mentor tools is an advantage.
• Excellent communication and interpersonal skills, and a team player attitude.

Who You Are:

A highly motivated individual with a passion for technological innovation and continuous improvement. You possess excellent problem-solving skills, a collaborative mindset, and the ability to work effectively within cross-functional teams. Your strong technical expertise and attention to detail enable you to deliver high-quality solutions in a fast-paced environment. You are committed to fostering an inclusive and diverse workplace, contributing to a positive and productive team culture.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team focused on advancing the capabilities of silicon IP integration. Our team collaborates closely with various functional teams within the logic library organization and tools teams to ensure the highest quality and performance of our standard cell libraries. We are committed to supporting each other and delivering exceptional results that drive Synopsys' leadership in the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.