Mixed Signal Design Verification Intern

Introduction:

We Are: "Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world."

Internship Experience:

"At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!"

Mission Statement:

"Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond."

What You’ll Be Doing:

• Setup UVM and VMM SystemVerilog testbenches to co-simulate mixed signal designs in both analog and digital coexist environment
• Analyze / verify the functionalities of SERDES
• Define and track verification test plans
• Debug simulation failures in both analog and digital domains
• Create top level analog testbenches for SERDES
• Perform physical layout reliability analysis for SERDES

What You’ll Need:

• Currently pursuing a bachelor’s degree in Electronic Engineering, Computer Science, or related field in the penultimate year of study
• Strong knowledge of analog circuitry such as bandgap, opamp, PLL, Transmitter/Receiver designs etc.
• Ability to write scripts in languages such as Perl, Python and Unix shell
• Familiar with Verilog and SystemVerilog

Key Program Facts:

• Program Length: 12-16 months
• Location: Mississauga, Canada
• Working Model: Hybrid
• Full-Time/Part-Time: Full-time
• Start Date: May 2025

Equal Opportunity Statement:

"Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us."