Background

High‑voltage (HV) gate drivers for automotive traction inverters increasingly rely on multi‑die architectures, where galvanic isolation is required to ensure safety and reliable operation. Efficient communication across isolated domains is essential to guarantee real‑time coordination, error robustness, and functional safety compliance.

Objective

The objective of this thesis is to design and verify a new digital architecture enabling communication and control between galvanically isolated dies within an HV Gate Driver IC. The work aims to overcome the limitations of the current implementation by introducing a dedicated communication protocol and enhanced control mechanisms.

Thesis Description

The project is structured into three main phases:

Architectural Analysis

Perform a detailed review of the existing communication architecture.

Identify structural limitations, performance bottlenecks, and operational constraints.

Define system‑level requirements for the next‑generation solution.

Digital Architecture Definition and RTL Implementation

Propose a new communication protocol optimized for isolated multi‑die systems.

Design advanced mechanisms for Synchronization, error detection, monitoring, and recovery

Arbitration of communication events over a single magnetic coil

Implement the proposed architecture in RTL, including Data encoding/decoding modules, Control units, Channel monitoring blocks, Recovery logic

Functional Verification (UVM)

Develop a UVM-based simulation environment.

Evaluate system performance in terms of: Latency, Throughput, Event collision handling

Validate protocol robustness and behavior under fault conditions.

Expected Outcome

The proposed work will establish the foundation for a new generation of HV Gate Drivers, enabling improved robustness, performance, and scalability of isolated multi‑die communication.

Candidate Profile

• Master’s Degree student in Electronic Engineering, Electrical Engineering, Computer Engineering or related field.
• Knowledge of digital design principles and RTL (SystemVerilog or VHDL).
• Familiarity with UVM or functional verification methodologies is a plus.
• Interest in automotive power electronics and mixed‑signal integrated systems.

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