2026 Intern - SOC RTL Design and Integration
NXP Semiconductors
Design
Pudong, Shanghai, China
Posted on Jul 8, 2025
Responsibilities：
- Work on SOC Front-end design team, be responsible for the SOC subsystem design, including subsystem integration, RTL coding, design rule check and constrain delivery.
- Requirement：
- Strong Verilog and C coding skills
- Good knowledge of digital IC design
- Familiar with on-chip bus protocols (AXI/AHB or similar) is a plus
- Good English communication skills.
Requirements:
- Strong Verilog and C coding skills
- Knowledge of on-chip bus protocols: AMBA, AXI or similar is a plus
- Extensive knowledge and experience in front-end implementation tasks such as constraint definition (timing & power), synthesis, power analysis, equivalence checking and STA is a plus
- Good English communication skills.