Define and write IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implantation specifications); write stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases; define and write System Verilog Assertion (SVA) cover properties to match the verification plan; write System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness; develop and maintain portions of a verification environment including scripts and Make files; debug failure testcases to determine source or failure (tool, testcase, checker, Verilog, RTL) and track resolution; collect code and functional coverage results from random simulations and analyze uncovered events to determine additional test scenarios needed 100% coverage; perform assertion-based formal verification of blocks and IPs to ensure requirements met.

Qualifications:

Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, foreign equivalent or related field.

Three (3) years of experience in the job offered, Senior Engineer – Verification, Research Assistant, Design Verification Engineer or similar occupations.

Required skills:

Position requires three years (3) years of experience in:

• Programming languages (C, SV, Verilog, UVM, Python, Perl);
• Knowledge of VCS/Verdi tool;
• IP Design, Verification ;
• Test planning ;
• Test case;
• Testbench;
• Simulation; and
• Debug.

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.