NXP's MCU/MPU Engineering (MME) team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for NXP's Automotive, Secure Edge, Advanced Analog and Radar Processing business lines. MME's. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low power devices to highly-integrated, high performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards

Responsibilities:

• Develop and implement DFT architectures and methodologies for advanced SoC designs, focusing on achieving high test coverage and minimizing test time.
• Drive DFT strategy and planning for new projects, collaborating closely with design, verification, and physical design teams to ensure seamless integration of DFT solutions into the overall design flow.
• Lead DFT implementation activities including scan insertion, ATPG (Automatic Test Pattern Generation), BIST (Built-In Self-Test), and boundary scan (JTAG) insertion.
• Perform DFT verification and sign-off, including scan chain simulations, stuck-at and transition fault simulations, and DFT coverage analysis.
• Work closely with Test Engineering Team to ensure successful manufacturing test bring-up and production test program development.
• Investigate and resolve DFT-related issues encountered during silicon bring-up and production testing, collaborating with cross-functional teams to implement effective solutions.
• Stay updated on the latest industry trends and advancements in DFT methodologies and tools, drive continuous improvement initiatives to enhance DFT efficiency and effectiveness.
• Mentor junior engineers and provide technical guidance and expertise in DFT methodologies and best practices.
• Experience with Siemen's Scan Streaming Network (SSN) highly desirable

Requirements:

20+ years of industry experience in DFT engineering, with a proven track record of delivering successful DFT solutions for complex SoC designs. Lead the DFT Organization at Candidate’s site and will be responsible for driving DFT tasks of multiple products from definition to bring up stages including:

• DFT Insertion in RTL for MBIST, SCAN, IO, LBIST.
  SSN and TK based multi-vendor Scan chain insertion
• Self-test for IN-system test
• DFT verification including PA-RTL, GLS for various modes implemented.
• ATPG flow-based pattern generation.
• Timing constraints ownership for DFT modes.
• Post-silicon planning and bringup

Preferred Qualifications:

• Master's degree in Electronics engineering, Electrical Engineering, Computer Engineering, or related field.
• Experience with advanced DFT techniques such as hierarchical DFT and low-power DFT.
• Familiarity with DFT automation and scripting languages such as TCL, Perl, or Python.
• Knowledge of post-silicon DFT activities such as test pattern compression and silicon bring-up.
• Previous experience in mentoring junior engineers and leading DFT projects..

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