Position Title -

Senior Lead Design Engineer -PDV & PDN

Key Responsibilities

• Would be responsible for hands-on physical verification and/or IR drop-EM closure of SoC's.

• Evaluate and deploy the evolving physical verification and/or IR-EM methodologies to handle

increasingly complex SoC/IP designs within aggressive, market-driven schedules

• Ensure quality adherence during all stages of the project life cycle. Drive thorough analysis of

existing processes and recommend and implement the process improvements to ensure ‘Zero

Defect’ chips

• Enable technological innovations from day to day learning & project experiences

• Actively work as part of team both locally & also with remote or multi-site teams

Key Skills:-

Self-starter with 5-12 years of experience on Chip level physical verification and/or IR drop-EM

on multimillion Gate and complex design with minimal supervision.

• Physical Verification requirements:

-Hands on experience of full chip run setup, analysis & singoff

-Deep knowledge of LVS, DRC, ERC , soft check, PERC , DFM etc

-Ability to debug physical verification issues independently

• IR drop & EM analysis requirements:

- Hands on experience of full chip & blocks level run setup, analysis & signoff

-Deep knowledge of concept behind IR drop & EM(electromigration) as well as power grid design - Ability to debug IR & EM issues independently

• Good control over scripting languages like PERL/TCL/Python is MUST.

• Working knowledge of floor-planning/APR tool is an added advantage

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