Role description, accountabilities

This position consists in:

• Leading micro-architecture, RTL design and integration of a System on Chip (SOC) or SOC sub-system, from requirements specification to tape-out and beyond,
• Delivering signed-off system verilog RTL and associated deliverables (e.g. UPF, CDC/RDC constraints, design documentation)
• Working with different functions like architecture, verification, DFT, physical implementation, silicon validation, etc. to reach quality silicon products, meeting schedule objectives.

Job skills & prerequisites

Senior digital IP or SoC design engineers with solid experience in all aspects of RTL design flow i.e. from specification to micro-architecture, RTL design, verification, timing analysis and DFT concepts (scan, mbist).

The candidate should have a strong experience in RTL design, SOC integration, RTL signoff tools (CDC/RDC/Lint/Synthesis), and good knowledge of micro-processor or micro-controller (ARM or RISC-V) architectures, as well as ARM-Amba bus protocols.

Below are key topics that candidate would have to deal with:

• ARM CPU/MCU architectures,
• Clock and reset infrastructure,
• Low-power features and UPF modelling,
• Interconnects, virtualization,
• Trustzone security,
• Coresight infrastructure for debug/trace,
• Communication/control peripherals like PCIe, USB, DDR,
• Functional safety applied to digital SOC design,
• Coherency protocols,
• Scripting languages (e.g. Python or Perl)

Candidate would be integrated in a team based in France (Grenoble or Valbonne) and with day-to-day interactions with other design teams based locally or abroad. Therefore, ability to collaborate effectively across organizational and geographical boundaries is key.

Fluent written and verbal communication in French or English is needed.

Education & seniority

MSc/PhD in Electrical or Computer Engineering with at least 10 years experience in digital IP or SOC design.

More information about NXP in France...