Ready to join the future of innovation in SOC Physical Design?

This opening is within the Microprocessor and Microcontroller Engineering (MME) SoC Implementation Organization, a central Physical Design group responsible for end-to-end Physical implementation of the Automotive and Industrial Automation Processors in NXP. This is a dynamic team with operations in 7 locations around the world. In this role, you will have deep exposure and involvement in the full RTL2GDS flow, the ability to interact and collaborate with colleagues in USA, India and China on methodologies, efficiencies and new innovations.

Your responsibilities

• Responsible from RTL synthesis to GDS implementation and optimization of design including floorplanning, routing, timing convergence (STA) including related design ECO and physical verification for fulfilling all Technology & reliability related rules, such as DRC/LVS/Electromigration/IR drops.

• Contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.

• Physical Design (Synthesis, Place& Route, Timing closure) of key critical subsystem implementation.

• Static Timing Analysis (STA), includes working with the architecture and front-end designers for timing changes, create and verify constraints, perform hierarchical timing budgeting and analysis, create ECOs and drive timing closure for sub-system and SOC.

Your team

NXP MME SOC-Implementation team is a highly productive and dynamic organization which has a track record of successful product development and innovation. We are a diversified team with high energy, an open collaborative environment and eagerness for continuous improvement. Innovation is strongly encouraged as evidenced by the track record of invention disclosures.

The SOC implementation team is 300+ engineers strong across 7 sites in 3 different geographies. Each site reports directly to the leader of the implementation organization. The team has strong linkages to the architecture, RTL, DFT and IP teams within MME. There are additional linkages with the Technology, Design Enablement, Packaging and IT organizations. The product development of a large significant portion of NXP roadmap comes out of the MME organization and consequently there is remarkably high visibility to the NXP Management team.

Your profile

To be successful in this role you must have:

• BS or MS in Electrical or Computer Engineering.

• Expertise in Physical Implementation (Place&Route).

• Expertise in deep sub-micron CMOS process technology.

• Knowledge of Middle-End tasks (Synthesis, STA, LEC...) is a plus.

• Strong analyzing skills and problem-solving attitude.

• Effective communication skills to operate in a global environment.

• Strong automation skills with Perl, TCL...