Responsibilities:

• Collaborate in defining the Design for Testability (DFT) features and architecture for sophisticated System on Chip (SoC) designs.
• Develop DFT logic and circuits, encompassing Serial Access Non-Destructive Testing (SCAN), Boundary SCAN, Memory Built-In Self-Test (MBIST), and Analog Macro test logic.
• Create and manage DFT-related timing constraints, assisting backend engineers in achieving timing closure.
• Oversee the generation of DFT test patterns, as well as their simulation and debugging processes.

Requirements

• Minimum of 2 years of experience in DFT design and verification, with a focus on test pattern development.
• Strong understanding of DFT methodologies, including Scan/Automatic Test Pattern Generation (ATPG), MBIST, and Boundary Scan.
• Familiarity with DFT architectures such as JTAG, Scan compression techniques, scan chain insertion, and verification, as well as analog testing strategies.
• Proficient understanding of digital SoC design principles, including Static Timing Analysis (STA), verification, and Register Transfer Level (RTL) coding.
• Mastery of hardware description languages, particularly Verilog.
• Demonstrated commitment to meeting project schedules and maintaining high-quality work standards, with a strong team-oriented approach.
• Excellent English communication skills, both written and verbal.

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