Sr Director, IP Design Engineering (MSIP and Digital)

Job Responsibilities:

• Drive architecture definition in conjunction with the Systems Architects, and working with the cross function teams both on Design, Verification, Validation and supporting SW/FW teams.
• Drive compliance testing and assuring quality, meeting KPI’s and target performance.
• Play key team member role in SOC & digital IPs development from Micro-Architecture to RTL implementation
• Hands on involvement in IP & SOC digital design/Integration
• Translate Micro-Architecture specification to Implementation specification.
• Actively drive in technical challenges discussion and decision making within IP scope.
• Delivery of SOC with first time right quality meeting project schedule
• Grow the team appropriately to meet the roadmap requirements within cost constraints
• Raise the bar in terms of project execution
• Develop the team to ensure the next level of technical leaders and managers
• Will be the technical driver for a large BL; participates in Business roadmap / strategy.
• Influences technical strategy to drive innovation, e.g., products, technology and/or patents) that consistently contributes to significant revenue and profit. Enables new business opportunities.
• Accountable for the creation of current or future value through research, development, profitability / cost improvement, and/or capital avoidance that influences the Business group.

Job Requirements:

• BSEE required, MSEE preferred with 15+ years of industry related experience
• Ability to lead and motivate technical teams to develop industry-leading IP using cutting-edge methodologies

• Must have experience in ASIC/SoC front-end (preferably RTL Verilog and VHDL based) design and methodologies
• Earlier experience with SoC Processor based architectures needed. ARM experience would be added advantage
• Self-driven and capable for independent work and independent decision making.
• Knowledge in frontend design experience on IPs involve ARM processor based sub-system, Serial Standard interfaces, Memory controller
• Exposure to Low-power design, System Security considered as added advantage
• Hands on front-end design of complex multi clock domain blocks
• Fluency in design & verification languages such as VHDL, Verilog, C and System Verilog.
• Experience in Spyglass for lint and CDC checks.
• Experience in using Cadence RC for synthesis and LEC flow.
• Experience in identifying and implementing complex ECO in netlist.
• Knowledge on Verification Methodologies to actively participate in Debug Analysis
• Develop new IP and enhance existing IP and sub-systems.
• Develop both foundation IP and differentiating/market-oriented IP and maintain forward looking roadmaps
• Be recognized as an industry wide thought leader and technical authority with advanced knowledge of theories and concepts to evaluate and integrate critical information from different functions to inform the development of strategy and commercial objectives.

Location:

• This position may be located in Austin, TX or San Diego, CA

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.