Backend Design Engineer - IC (Analog & IP characterization)
Nokia
Nokia Bell Labs Core Research: Platforms & ASIC Research Team is seeking a talented and detail-oriented Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of Circuit Design/simulation of analog components (PLL & power management circuits etc.) and IP characterization of Digital Hard IPs. You will lead the design/development & characterization using your experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions.
The mission in Bell Labs Core Research is to invent game changing innovations at the edge of science in and across all network segments that define the future of communication, ensure portfolio leadership of Nokia’s business groups and create broader value in adjacent opportunities. The Platform and ASIC Research Lab teams focuses on access technologies, generate innovations and accelerate commercial adoption through implementation, experimentation, trials and technical demonstrations.
Nokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world.
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- Flexible and hybrid working schemes
- A minimum of 90 days of Maternity and Paternity Leave, with the option to return to work within a year following the birth or adoption of a child (based on eligibility)
- Life insurance to all employees to provide peace of mind and financial security
- Well-being programs to support your mental and physical health
- Opportunities to join and receive support from Nokia Employee Resource Groups (NERGs)
- Employee Growth Solutions to support your personalized career & skills development
- Diverse pool of Coaches & Mentors to whom you have easy access
- A learning environment which promotes personal growth and professional development - for your role and beyond
Backend Design Engineer to join our IC (Integrated circuit) development team. Will be responsible for Circuit Design/simulation of analog components (PLL & power management circuits etc.) and IP characterization of Digital Hard IPs. Will lead the design/development & characterization with industry-standard tools.
You have:
- Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred)
- 8+ years of experience in Circuit design, simulation and characterization of IPs & full custom circuits, functional simulations and statistical analysis.
- Experience with tape-out of designs for advanced nodes is highly desirable.
- Strong understanding of integrated circuit operation and CMOS fundamentals including process variation and statistical characterization at advanced process nodes 5nm 3nm etc.
- Proven expertise in IP characterization and Liberty modeling, a deep understanding of various Liberty formats including NLDM CCS ECSM LVF EM Aging and others.
- Experience with industry standard design & characterization solutions such as Virtuoso, Liberate or Siliconsmart/Primelib.
- Proficient in automation skills using Tcl Python and shell scripting to streamline characterization workflows.
It would be nice if you also had:
- Experience with Memory or Macro or AMS IP characterization is a plus.
- Familiarity with circuit design of PLLs & power management circuits, circuit testing & characterization is desirable.
- Design and implement high-performance circuits for frequency synthesis and clock generation.
- You will also work as an Engineer for Liberate, you will engineer innovative and quality characterization solutions/methods for foundational IPs, working closely with R&D and fellow engineers.
- Characterize parametric performance of High-Speed IO PHYs (SERDES), PLLs and other Custom/Foundational Hard-IPs.
- Work on different Liberty formats: NLDM, CCS, ECSM, LVF, EM, Aging etc.
- Contribute to industry-standard circuit simulators & perform characterization.
- Collaborate with design, verification, and research teams across the globe to resolve design challenges and improve performance.
- Work closely with foundry teams to address process technology issues and implement best practices