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People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

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Job Description:

• Technically independence in ASIC design implementation domain, which may include stages from design specification understanding till timing signoff for tape out
• To develop and signoff I.C. design projects RTL2GDS implementation and flow improvement. Responsibilities include (as applicable)
  • Effective and efficient synthesis implementation
  • Derive timing constraints from design spec, review and validate with respective designer/lead for signoff
  • Design-For-Test (DFT) implementation, covering basic scan insertion, compression, LOC/LOS and RAMBIST
  • Performing Floor planning, power planning, Placement, CTS and routing Optimization to meet PPA targets.
  • Ensure physical verification sign off DRC, LVS, IR drop, EM checks for both static and dynamic scenarios.
  • Low power design; vector-driven synthesis/layout optimization and leakage/dynamic power control techniques
  • Solving challenges, with problem-solving and critical thinking capability
  • Drive for Best-in-Class design implementation approach/process

• To document I.C. Design implementation and work procedures
  • Capturing design implementation approach, consideration, challenges and solutions employed using corporate template documentation
  • Complete audit and checklist fill-in, review and closure in compliance to corporate Design Control Procedures (DCP)
  • Filing issues, solution details and review confirmation in project ticketing system (PEPS) or CAD ticketing system (JIRA)

• To interface with
  • Project lead, RTL design and ATPG team on project related issues
  • CAD/TA on flow methodology

Requirements/Qualifications:

• Bachelor’s/master’s degree in electrical/Electronic Engineering, with 5-8 years of ASIC I.C. Design working experience
• Cadence Genus or Synopsys Design Compiler intermediate working experience
• Cadence Tempus or Synopsys Primetime intermediate working experience
• Cadence Innovus or Synopsys IC Compiler intermediate working experience
• Cadence Pegasus for signoff physical verification and Ansys Redhawk-SC for power integrity and EM/IR analysis

Added advantage

• Exposure to 7nm and below advanced process nodes
• Strong scripting skills in Perl, TCL, Shell or Python

Travel Time:

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.