Senior Engineer - Layout
Microchip Technology
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Job Description:
1. Contribute to physical layout of various memory chip circuit blocks, responsible for circuit block LVS/DRC verification.
2. Contribute to full chip level layout and verification, pattern fill and layer generation as well as tapeout process.
3. Learning the working knowledge of current CAD tools. Contribute to physical layout of various memory chip circuit blocks,
responsible for circuit block LVS/DRC verification.
Requirements/Qualifications:
1. Familiar with using Cadence Design Environment.
2. Understanding of basic CMOS design and process is a must.
Travel Time:
0% - 25%To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.