About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As an Analog IC Design Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.

What You Can Expect

• The candidate will be working on high-speed and high performance Analog SerDes development in advanced technology nodes, 3nm, 2nm and beyond.
• Participate in SerDes Architecture Development with DSP, Analog and Digital design teams.
• Interact closely with layout engineers to achieve required circuit performance.
• Working with the AE for the IP characterization and validation plan.
• Supporting IP Lab characterization and debugging.

What We're Looking For

• Bachelor’s degree in electrical engineering or related fields and 8+ years of related professional experience. Master’s degree and/or PhD in Electrical Engineering or related fields with 6+ years of experience.
• In depth understanding of transistor level CMOS analog circuit design and basic building blocks (BGR, Current mirrors, op-amps, feedback circuits etc )
• Experience in implementing Serial link building blocks for Tx / Rx (Driver, CTLE, FFE etc ) and clock path circuits (DLL' s, phase rotators etc);
• Know-how of resonant clocking and inductor-based circuits is a plus.
• Experience in optimizing FinFET CMOS layout to minimize parasitic
• Knowledge in Verilog-A for analog behavioral modeling / simulation data capture
• Strong written, Oral communication with a drive to continuously learn and grow.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-RV1