About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a Digital IC Design Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers.

This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.

What You Can Expect

Test our custom and semi-custom Marvell products using our custom test architectures. Focus on end-to-end Design-for-test (DFT) solutions from architecture, implementation, verification, and mass production readiness (MPR). Complete DFT insertion in RTL and meet high test coverage and low DPPM requirements. Perform verification, which includes Synopsys spyglass checking, design rule checks as well as ATPG simulations. Work closely with the Physical Design (PD) team on the physical implementation of DFT structures and timing team to close the SOC design. Leverage the latest techniques, methodology, automation, and tools in the latest technologies (5nm, 3nm, 2nm). Work with test and product engineering teams to support hardware debug and test time for MPR of design.

What We're Looking For

Bachelor’s or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field and five (5) years of experience in the job offered or related occupation.

Experience must include four (4) years with each of the following:

• ASIC-DFT Architecture design & implementation.
• Pre-Silicon RTL & GL validation of DFT implementation.
• Running formal verification rules on DFT structures and validation of the same.
• Verilog testbench development.
• Automation of the DFT flow.
• SSN Integration at block level & planning at top level.
• Test coverage improvement with different techniques.
• Debugging timing violation with STA team.
• Post-silicon validation for different fault models and production test features.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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