About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Marvell post silicon validation group designs and develops test platforms for validating multi-core Arm-based Network processors used in many communication infrastructure applications such as 5G base stations and cloud computing platforms. The electrical characterization team is a post silicon validation sub-group focused on the debug and characterization of SerDes and DDR interfaces on the processor. The SerDes interface use NRZ and PAM4 signaling for Ethernet, CPRI, JESD, and PCIe interfaces. DRAM interfaces include LPDDR5, DDR4/5 memory modules.
Characterization engineers are responsible for developing test platforms used and automated test suites to characterize the analog interfaces over process voltage and temperature (PVT) extremes to determine silicon viability for volume production.

What You Can Expect

You will be and be asked to help with characterization and SoC validation of PCIe on our next generation Solid State Disk Drives.
Analyze the test results and generate professional validation reports.
Work with analog and digital circuit designers to identify design issues.
Provide technical support to Field Application Engineers who support customers.
Provide technical support to Test Engineers who design tests for mass production.
You must be highly energetic and self motivated and should be able to work on a given task independently.

What We're Looking For

We are looking for hardware validation engineer with experience in:
• PCIe protocol, architecture and electrical standards
• PCIe clocking architecture, reset schemes, power management, speed change, and equalization
• PCIe subsystem (PHY + MAC) and PIPE interface
• PCIe silicon bring-up, validation, and debug using exercisers and analyzers
• PCIe characterization and compliance test using standard lab equipment
• PCIe system interoperability
• Experience in system bring-up, validation, and debug with root-cause analysis
• Experience developing FW code (C programming) for system bring-up, validation, and debug

• Experience developing Linux drivers
• Experience using standard lab equipment, including logic analyzers and oscilloscopes
• Experience writing scripts (Python or others) for silicon test and lab automation
• Familiar with CXL , NVMe and SSD Controllers is a plus
Good communication skills in English, written and spoken.
Candidate should be flexible, proactive and have the ability to work in a team

Expected Base Pay Range (USD)

143,200 - 214,500, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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