About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell’s Compute and Custom Solutions Business Unit develops cutting-edge semiconductor solutions in the most advanced technologies. Our focus is on solving the most difficult design problems in the areas of AI, wired and wireless communications, and other infrastructure applications. The CCS is looking for an Digital SOC design engineer with a demonstrated track record of success in launching products with specific expertise in PCIe and CXL technologies.

What You Can Expect

In this role, you will:

• Shape the micro-architecture of the chip

• Write specifications and define micro-architecture of the design

• Implement designs using low-power RTL coding techniques

• Collaborate with the verification team on the verification test plan, coverage analysis, and full-chip simulation plus debug

• Write SVA assertions for dynamic simulation and apply them in formal verification

• Prepare and present design reviews

• Work with the physical design team in aiding the implementation of the functional blocks

• Interact with the project manager to scope and assign tasks

• Provide reasonable and accurate schedule estimates and follow through to meet them in spite of surprises

• Proactively communicate challenges and provide contingency plan recommendations to management

• Work with multiple design centers and design groups to shape future methodology

• Support the post silicon team to bring up silicon in the lab

• Work with the software team to ensure product meets customer use cases

• Provide expert product support in post-silicon debug environments

What We're Looking For

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Or Master’s degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience. Or PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience.

To be successful in this role you will need the following skills:

• Fluent in System Verilog RTL coding techniques.

• Experience in high speed, multiple clock domain designs

• Expertise in PCIe, CXL protocols

• Familiar with modern SoC architectures and various interface technologies such as AXI, DDR, Ethernet, PCIe.

• Experience in micro-architecture of complex custom/ASIC products involving Chip I/O, shared memory, and embedded processors

• RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.

• Experience in designing high speed (>1 GHz)/high-performance embedded processor SOC products is a plus.

• Experience in implementation/timing closure for high speed design.

• Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies.

• Ability to create SVA assertions and apply formal verification concepts and tools

• Ability to come up with creative and innovative solutions, and display technical leadership from within a team of engineers

• Excellent verbal and written communication

• Discipline and rigor in documentation

• Ability to work efficiently and influentially with team members across multiple sites

• Enthusiastic about exploring and applying new methods, tools, and process efficiency to ASIC design flow

• Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is desirable.

#LI-TM1

Expected Base Pay Range (USD)

162,000 - 239,760, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.