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Analog Design Engineer, Principal



Santa Clara, CA, USA
Posted on Saturday, February 10, 2024

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

CE-AMS - Join a world-class analog design team providing high performance analog and mixed mode circuits for industry-leading Networking and Automotive Ethernet products. Candidate will have opportunity to architect and design circuits for high performance transceivers and other critical analog functions, and lead a team of analog design engineers.

What You Can Expect

  • Analog circuit design, such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.).

  • New technique development for next generation SERDES
  • Project leading and management
  • Analog layouts supervise with advanced process node
  • System verification and circuit design spec creation
  • Silicon bring-up, debug and support
  • Team communication and documentation

What We're Looking For

Master’s degree and/or PhD Preferred in Electrical Engineering or related fields with 8+ years of experience.

  • Should have strong analog design fundamentals and experience in designing analog circuit blocks such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.).
  • Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must
  • Knowledge of the fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution.
  • Good understanding of analog layouts in FinFet and its effect on high-speed designs
  • Experienced in system level pre-tape out analog validation
  • Experienced in lab chip bring-up and debugging efforts
  • Strong communication and documentation skills
  • Technical management experience is a plus


Expected Base Pay Range (USD)

144,180 - 216,000, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at