Keysight is on the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.

Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.

Keysight is looking for a highly motivated FPGA / RTL Design Intern (VHDL / Verilog / SystemVerilog) to join our engineering team and contribute to the development of high-performance FPGA-based systems.

This role is ideal for candidates passionate about low-level hardware design, working close to silicon, and building real digital systems used in advanced test and measurement solutions.

• Design and implement RTL for FPGA-based systems using VHDL, Verilog or SystemVerilog
• Develop and execute testbenches for functional verification
• Work with FPGA toolchains (Xilinx Vivado, Intel Quartus) from synthesis to implementation
• Integrate, debug and validate designs on real FPGA hardware (e.g. Zynq, RFSoC or similar platforms)
• Analyze and optimize designs for timing closure, latency and resource utilization
• Collaborate with engineers on signal processing, high-speed interfaces and system integration

• Currently pursuing a degree or master’s in digital electronic, Electrical Engineering or a related field
• Hands-on experience with FPGA development
• Experience writing RTL (VHDL, Verilog or SystemVerilog)
• Experience with simulation and testbench environments (ModelSim, QuestaSim or similar Simulators)
• Familiarity with FPGA tools such as Vivado or similar
• Experience implementing and validating designs on real FPGA hardware

Candidates must be able to demonstrate at least one end-to-end FPGA project beyond coursework
(design → simulation → implementation → validation)

Nice to have:

• Knowledge of AXI / AXI4 / AXI-Stream interfaces
• Experience with SoC FPGA platforms (Zynq, RFSoC)
• Background in signal processing, DSP or RF systems
• Experience with timing closure and optimization
• Programing languages: Python, C++
• Hands on experience working in HW set-up and debugging

Additional information:
This role does not offer visa sponsorship. Candidates must have the right to work in Spain at the time of application.