CA Pay Range (Annual):

At Infinera, your base pay is one part of your total compensation package. Your actual base pay will depend on your skills, qualifications, experience, and location. This role may be eligible for equity grants, discretionary bonuses, or commission payments. The amount of these incentives is based on the terms of the Company’s incentive plans, the Company’s financial performance, and/or individual employee job performance.

Infinera also offers paid leave, medical,

dental, and vision coverage, 401(k),

life, and disability insurance to eligible employees.

The successful candidate shall possess the capability to design and analyze high speed, high performance analog / mixed signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design all the way to production.

Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users.

If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera!

Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry.

Essential Functions and Key Responsibilities:

• Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs;
• Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary;
• Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc.
• Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality;
• Need to support and comply with the team’s design methodologies and release flows.

Mandatory Knowledge/Skills/Abilities:

• Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.
• Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies.
• Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production.
• Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis;
• Must have a good understanding of device physics and the impacts of layout effects;
• Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS;
• Collaborative with other local or remote team members in a fast-paced professional environment.

Preferred Knowledge/Skill/Abilities:

• Fluent in verbal and written communications;
• Independently resolves issues and conquer design challenges;
• Self-motivated and detail-oriented;
• Has the knowledge of (optical) communication theories and Matlab coding.

Education and Experience Requirements:

• Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

#LI-SR2

“This position requires direct or indirect access to certain confidential information, hardware, software, technology, or technical information (referred to here as “Export-Controlled Information”) controlled under the U.S. International Traffic in Arms Regulations (ITAR) and/or the U.S. Export Administration Regulations (EAR). All personnel in this position must be eligible to or be able to obtain authorization from the appropriate agency to access applicable Export-Controlled Information. The U.S. Department of Commerce currently requires a foreign person with a most recent citizenship or permanent residency of Sudan, Ukraine, or a country currently designated in Country Group D:1, E:1 or E:2 (Supplement No. 1 to Part 740, Title 15) to have an export control license to access our Export-Controlled Information, unless they meet certain exemptions provided under U.S. export control laws and regulations. The list of applicable countries in Country Group D:1, E:1 or E:2 may be updated by the U.S. government from time to time. The current processing time for an export control license is approximately 4 to 6 months.

Your employment or engagement with Infinera shall be contingent on verifying your eligibility or requirement for obtaining a necessary license and/or authorization from the appropriate agency. You will be required to provide certain information for export control compliance assessment purposes, and your information will be reviewed by Infinera's hiring and export control teams to ensure compliance with the U.S. export control laws and regulations. Infinera will collect necessary documents (such as proof of citizenship etc.) to assess license/authorization requirements if you are offered and accept the position.”

Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment.