Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users.

If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera!

Engaging in the design and implementation of the high-speed, high-performance analog / mixed-signal verifications, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high-speed transmission.

Essential Functions and Key Responsibilities:

• Model the circuit blocks and mixed-signal IPs, including but not limited to high-speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system-level performance.

• Perform the functional verification and timing analysis on the IPs and the blocks.

• Work with the digital verification team to generate the adequate interface to ensure the timing and connectivity.

• Performs co-simulations on analog blocks and digital blocks in the mixed-signal simulation environment.

Mandatory Knowledge/Skills/Abilities:

• Has intimate knowledge of UVM verification flow.

• Have prominent tracking record in modeling and verification of analog/mixed-signal IPs, including but not limited to SERDES, optical links, and wireless transmission systems.

• Hands-on in modeling and simulating with System-Verilog (WREAL), Verilog-AMS, and/or C, C++.

• Have a decent understanding in CMOS analog / mixed signal design.

Preferred Knowledge/Skill/Abilities:

• Able to create IBIS-AMI model.

• Can code in System-Verilog (WREAL).

• Fluent in verbal and written communications.

• Independently resolves issues and conquer design challenges.

• Self-motivated and detail oriented.

• Has good interpersonal skills.

Education and Experience Requirements:

• Minimum Requirement of Staff Engineer: M.S. in E.E. with 8+ years’ experience, or Ph.D. in E.E. with 6+ years’ experience

• Minimum Requirement of Principal Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience