Join a highly skilled team advancing the verification of industry‑leading Field‑Programmable Gate Array (FPGA) technologies that power high‑speed, next‑generation networks. This role drives chip‑level verification excellence, influences methodology and architecture, and ensures the delivery of robust, high‑quality designs that strengthen Ciena’s position as a global leader in adaptive networking.

How you will make an impact:

• Establish verification methodology, architecture, and infrastructure, including models, generators, monitors, and scoreboards

• Define test priorities and coverage targets in close partnership with design teams

• Develop comprehensive verification plans aligned to program milestones

• Create and execute directed and constrained‑random testcases using SystemVerilog and the Universal Verification Methodology (UVM)

• Triage regressions, generate detailed reports, and drive resolution of defects

• Mentor junior verification engineers on verification strategies and best practices

• Provide accurate schedule estimates and maintain clear communication with project stakeholders

The must haves:

• Bachelor’s degree in Engineering (or equivalent experience)

• Minimum 8 years of FPGA or Application‑Specific Integrated Circuit (ASIC) verification experience

• Hands‑on expertise developing testbench environments using SystemVerilog and the Universal Verification Methodology (UVM)

• Strong debugging and problem‑solving skills

• Experience with both directed and constrained‑random stimulus generation

• Working knowledge of Linux/Unix and PC operating environments

• Experience with Mentor Graphics Questa and Synopsys VCS verification tools

• Familiarity with industry‑standard interfaces such as Peripheral Component Interconnect Express (PCIe), Inter‑Integrated Circuit (I²C), Serial Peripheral Interface (SPI), and a solid understanding of Optical Transport Network (OTN) as well as Ethernet packet structures and interfaces including CAUI, XLAUI, XAUI, and XFI

Nice to haves:

• Strong communication skills with the ability to convey complex technical concepts clearly

• Demonstrated ability to collaborate effectively across multidisciplinary teams

• Experience guiding or coaching less‑experienced engineers

• Highly organized, detail‑oriented approach to project execution

• Creativity in problem‑solving and methodology development

Pay Range:

The annual pay range for this position is $103,700 - $165,700 CAD.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.